1. Technical Field
The present disclosure relates to a semiconductor integrated device with mechanically decoupled active area, and to a related manufacturing process.
2. Description of the Related Art
The drift of electrical parameters is a very critical issue affecting semiconductor integrated devices; this drift is commonly due to mechanical deformations (e.g., bending) of the semiconductor die (or dice) within the package of the devices, due to stresses induced by the same package. This issue is especially critical in case of electronic components such as OA (Operational Amplifiers), ADC (Analog to Digital Converters), voltage regulators, or the like, where a desired value of relevant electrical quantities has to be kept accurately stable with time; or in case of micromechanical structures, whose mechanical properties directly affect the performances of the integrated devices.
As it is known, an integrated device includes one or more dice of semiconductor material (e.g., silicon), in which electronic circuits (e.g., an ASIC—Application Specific Integrated Circuit) and/or microelectromechanical structures are made (in the case of MEMS—MicroElectroMechanical Systems), and which are encapsulated in a package, protecting and covering the dice and providing suitable electrical connections to the outside, e.g., for soldering to an external printed circuit board. Common packages are the so called SO or SOIC (Small Outline Integrated Circuit) packages, or the BGA (Ball Grid Arrays) or LGA (Land Grid Array) packages, which offer reduced area occupation and high density of the external electrical contacts.
FIG. 1 schematically shows an example of an integrated device with a SO package, denoted as a whole with 1, provided with a die 2 and a package 3 enclosing the die 2. Die 2 may include a micromechanical detection structure and/or an ASIC including electronic circuits (clearly, the integrated device 1 may also include several dice, arranged in known stacked or side-by-side configurations); in a manner not shown, die 2 includes a body of semiconductor material, including an active portion wherein electronic components or micromechanical structures are formed, and overlying layers of metal and/or dielectric (passivation) materials.
Package 3 includes a die-carrier 4 (usually referred to as “die pad” in similar packaging structures and having a support function for the die 2), having an internal surface 4a to which the die 2 of the integrated device 1 is attached via an adhesive layer 5, e.g., a glue or a tape (usually referred to as “die attach film”), and an external surface 4b, which may also define an external surface of the package 3, or, as in the example shown, be arranged inside the package 3.
A coating and protecting material, generally a mold compound 6, e.g., a resin material, covers and surround the die-carrier 4 and the die 2 (in particular, top and side surfaces thereof, where the die 2 is not attached to the die-carrier 4), protecting the same from the external environment.
Suitable electrical connections in the form of wires 7 (using the so called “wire bonding” technique) electrically connect the die 2 to a lead-frame 8, carrying electrical contacts, so called leads 9, protruding outside the package 3 (and the mold compound 6) for the electrical connection to the outside, e.g., to an external printed circuit board (here not shown).
In particular, the die 2 is subject to mechanical stresses within the package 3, which result from the balancing of forces that the various packaging materials contacting the same die 2 (such as resin, glue, tape, die-pad) apply thereto; accordingly, and due to these mechanical stresses, bending of one or more surfaces of the die 2 may occur. In general, these forces are denoted as package-induced stresses and amount to encapsulation stresses and thermally-induced stresses due to the different thermal expansion coefficients of the various materials within the package.
A proposed solution to cope with this issue involves a suitable selection of the package materials (e.g., resin, die-pad, glue or tape) and their dimensions, and a proper designing of the die, e.g., in terms of the thickness of the semiconductor material. This approach basically amounts to an exercise of optimization, aimed at a joined selection of suitable materials and parameters that do not cause deformations, e.g., bending, of the semiconductor die, e.g., under thermal stresses, or in any case limit the same deformations.
Clearly, this solution is not robust against spreads of the properties of the package materials and dimensions, e.g., due to the packaging process or aging, which may not be taken into account at the design stage.